1. Field of the Invention
The present invention generally relates to structures formed with reflow materials and more particularly to tapered vias formed with reflow materials.
2. Description of the Related Art
Materials which change from a solid state to a semi-liquid or liquid state at a temperature lower than the phase transition point of a semiconductor are referred to as reflow materials and are used by the microelectronics industry for various applications. Various types of glasses or insulators, such as borophosphosilicate glass (BPSG) or boron doped glass (BSG) are commonly used as reflow materials.
An advantage of using reflow materials is that, because of their low melting temperature, the reflow materials can be heated to a liquid or semi-liquid state, which allows the reflow material to flow (i.e. become smooth or fill a void), without affecting the underlying substrate.
However, the control of reflow materials in very small structures and the relatively high dielectric constant of these materials, has limited their application in the manufacturing of very-large-scale advanced integrated circuits.
When forming vias (i.e., holes allowing electrical connection between different layers) in a substrate, it is desirable to open the vias through the inter-level dielectric (ILD) to selected local regions of the under layer conductor. Further, it is conventionally known to be advantageous to taper the sidewall angle of the vias so that the subsequent deposition of the conducting material will completely fill the contact hole and not leave voids or locally thin regions in the conductor.
Tapered-via contacts should preferably provide high yield, low cost, ground-rule scaling (i.e., be useable with very small structures) and a controllable contact resistance. Taper angles in the range of 60 deg-85 deg from the horizontal plane have been found to permit void-free deposition (i.e., filling) of conductor films in contact holes.
As mentioned above, it is desirable to maintain a low dielectric constant in the ILD and to reduce the capacitance between adjacent conductive patterns, and hence reduce the resistance-capacitance (RC) propagation delay associated with the circuit.
Conventionally, reflow materials were not used as tapered spacers in vias because controlling the reflow (i.e., the melting) of the reflow material is difficult an expensive, particularly with very small structures such as vias. Secondly, reflow materials conventionally have and undesirably high dielectric constant. These shortcomings limit the application of these materials in the manufacturing of very-large-scale advanced integrated circuits.
Further, blanket reflow materials are difficult to integrate with global planarization such as chemical-mechanical polishing (CMP). Blanket reflow materials also present depth-of-focus limitations when used in multi-layer interconnections.